[Zlib-devel] [7/6][RFC V2 Patch] Blackfin implementation

[Jan Seiffert]

2011/4/2 Mike Frysinger <vapier at gentoo.org>:
> On Sat, Apr 2, 2011 at 1:15 PM, Jan Seiffert wrote:
>> What is it with me, others read a good book, i read processor handbooks...
>>
>> Only compile tested, i don't know if this works (and i have my doubts,
>> this processor and the asm is ... funky...), but since it only took me
>> 5 hours.
>
> the asm is awesome ;).  i like being able to write standard C/math
> statements to express my math desires.
>

It has it's moments, but, uhm, first i was a little lost.

> just a quick peek ...
>
> +        "DISALGNEXCPT || %[lt0] = [I0 ++ %[m_4]];\n\t"
>
> just be sure, what are you going for here ?  you want to make sure you
> can support unaligned loads ?

Yes.
Saving myself all the foo with prealigning, then doing the main loop,
only to merge back at the end. This gives a lower start overhead and
makes all the length check easier. And with the low register count, if
i have to use r1:0 anyway, then i can do it in the way it is suposed
to be (with the byteunpack and it's "uses i0 lower bits to extract the
right bits"). I mean the CPU can do in HW what i would do in software
(kind of).

>  unfortunately, that isnt what DISALGNEXCPT does :(.  all it does is ignore the low bits of the index
> register when doing the load.
>

Thats exactly what i want, like the altivec loads, the only real use
full mode for memory accesses ;)
Lower address bits? Totally overrated...

But since i do not know any (instruction) timings, esp. when memory
access is involved, if you say to me "don't do this because..." I can
see what i can change.

> so if the pointer is like 0x1111, the hardware will turn this into
> 0x1110 before processing it.
>

Uhhh, only 1 bit is masked out? I thought it was 2?

> +        "LC1 = %2;\n\t" /* set hw loop counter */
> +        "%2 = 0;\n\t" /* s1s = 0 */
> +        "LOOP inner_add LC1;\n\t"
> +        /*=========================*/
> +        "LOOP_BEGIN inner_add;\n\t"
>
> usually this is done like so:
> LSETUP (inner_add_start, inner_add_end) LC1 = %2;
> inner_add_start: ....
> inner_add_end: ... last insn of the loop ...
>
> make sure %2 is a Preg of course.  reloading LB/LT/LC can take a bad
> cycle penalty when they're done independently.
>

Hmmm, ok, but a Preg?
I can't do any arithmetic on them.

>> Maybe someone has a Blackfin to test it on.
>
> the gnu sim should support linux userspace apps.  there is a qemu port
> too, but the insn coverage with more exotic insns isnt that great.
>
> $ echo 'main(){puts("hi");}' | bfin-linux-uclibc-gcc -static -x c - -o a.out
> $ bfin-linux-uclibc-run --env user ./a.out
> hi
>
> you can even trace the register state on each insn with the
> -t/--trace-core/--trace-insn options:
> insn:     0x00221e                       -R6 = P3;
> reg:      0x00221e                       -wrote R6 = 0x3b48
> reg:      0x00221e                       -wrote PC = 0x2220

Is there any chance to install it with crossdev?

> -mike
>
Greetings

Jan

-- 
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