[Zlib-devel] [7/6][RFC V2 Patch] Blackfin implementation

[Mike Frysinger]

On Sat, Apr 2, 2011 at 1:15 PM, Jan Seiffert wrote:
> What is it with me, others read a good book, i read processor handbooks...
>
> Only compile tested, i don't know if this works (and i have my doubts,
> this processor and the asm is ... funky...), but since it only took me
> 5 hours.

the asm is awesome ;).  i like being able to write standard C/math
statements to express my math desires.

just a quick peek ...

+        "DISALGNEXCPT || %[lt0] = [I0 ++ %[m_4]];\n\t"

just be sure, what are you going for here ?  you want to make sure you
can support unaligned loads ?  unfortunately, that isnt what
DISALGNEXCPT does :(.  all it does is ignore the low bits of the index
register when doing the load.

so if the pointer is like 0x1111, the hardware will turn this into
0x1110 before processing it.

+        "LC1 = %2;\n\t" /* set hw loop counter */
+        "%2 = 0;\n\t" /* s1s = 0 */
+        "LOOP inner_add LC1;\n\t"
+        /*=========================*/
+        "LOOP_BEGIN inner_add;\n\t"

usually this is done like so:
LSETUP (inner_add_start, inner_add_end) LC1 = %2;
inner_add_start: ....
inner_add_end: ... last insn of the loop ...

make sure %2 is a Preg of course.  reloading LB/LT/LC can take a bad
cycle penalty when they're done independently.

> Maybe someone has a Blackfin to test it on.

the gnu sim should support linux userspace apps.  there is a qemu port
too, but the insn coverage with more exotic insns isnt that great.

$ echo 'main(){puts("hi");}' | bfin-linux-uclibc-gcc -static -x c - -o a.out
$ bfin-linux-uclibc-run --env user ./a.out
hi

you can even trace the register state on each insn with the
-t/--trace-core/--trace-insn options:
insn:     0x00221e                       -R6 = P3;
reg:      0x00221e                       -wrote R6 = 0x3b48
reg:      0x00221e                       -wrote PC = 0x2220
-mike